C8051F352 Datasheet, PDF (136/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
17.4. System Clock Selection
The internal oscillator requires little start-up time and may be selected as the system clock immediately fol-
lowing the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typ-
ically require a start-up time before they are settled and ready for use. The Crystal Valid Flag (XTLVLD in
register OSCXCN) is set to ‘1’ by hardware when the external oscillator is settled. To avoid reading a
false XTLVLD, in crystal mode software should delay at least 1 ms between enabling the external
oscillator and checking XTLVLD. RC and C modes typically require no startup time.
The CLKSL[1:0] bits in register CLKSEL select which oscillator source is used as the system clock.
CLKSL[1:0] must be set to 01b for the system clock to run from the external oscillator; however the exter-
nal oscillator may still clock certain peripherals (timers, PCA) when the internal oscillator is selected as the
system clock. The system clock may be switched on-the-fly between the internal oscillator, external oscilla-
tor, and Clock Multiplier so long as the selected clock source is enabled and has settled.
SFR Definition 17.5. CLKSEL: Clock Select
R
R
R
R
R
R
R/W
R/W
Reset Value
—
—
—
—
—
—
CLKSL
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xA9
Bits7–2: Unused. Read = 000000b; Write = don’t care.
Bits1–0: CLKSL1–0: System Clock Select
These bits select the system clock source.
CLKSL
00
01
10
11
Selected Clock
Internal Oscillator (as determined by the
IFCN bits in register OSCICN)
External Oscillator
Clock Multiplier
RESERVED
Table 17.1. Oscillator Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Conditions
Internal Oscillator Frequency
Reset Frequency
Internal Oscillator Supply
OSCICN.7 = 1
Current (from V_DD)
Min Typ Max
24 24.5 25
— 450 —
Units
MHz
µA
136
Rev. 1.1