C8051F352 Datasheet, PDF (30/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics
–40 to +85 °C, 25 MHz System Clock unless otherwise specified.
Parameter
Analog Supply Voltage¹
Analog Supply Current
Conditions
Internal REF, ADC, IDACs,
Comparators all active
Min Typ Max Units
2.7 3.0 3.6
V
— 0.75 1.3 mA
Analog Supply Current with analog
sub-systems inactive
Internal REF, ADC, IDACs,
Comparators all disabled,
oscillator disabled
—
<1
—
µA
Analog-to-Digital Supply Delta
(|V_DD – AV+|)
Digital Supply Voltage
—
— 0.5
V
2.7 3.0 3.6
V
Digital Supply Current with CPU
active
V_DD = 2.7 V; SYSCLK = 25 MHz —
V_DD = 2.7 V; SYSCLK = 50 MHz —
V_DD = 3.3 V; SYSCLK = 25 MHz —
V_DD = 3.3 V; SYSCLK = 50 MHz —
9.9 11.3 mA
17.8 20.0 mA
13.6 15.5 mA
24.9 27.1 mA
Digital Supply Current with CPU
inactive (not accessing Flash)
V_DD = 2.7 V; SYSCLK = 25 MHz —
V_DD = 2.7 V; SYSCLK = 50 MHz —
V_DD = 3.3 V; SYSCLK = 25 MHz —
V_DD = 3.3 V; SYSCLK = 50 MHz —
5.7 6.6 mA
11.1 12.7 mA
7.5 8.5 mA
15.0 16.5 mA
Digital Supply Current (shutdown)
Oscillator not running
— < 0.1 —
µA
Digital Supply RAM Data Retention
Voltage
SYSCLK (System Clock) ^2,3
Specified Operating Temperature
Range
— 1.5 —
V
0
—
50 MHz
–40 — +85 °C
Notes:
1. Analog Supply AV+ must be greater than 1 V for V_DD monitor to operate.
2. SYSCLK is the internal device clock. For operational speeds in excess of 25 MHz, SYSCLK must be derived
from the internal clock multiplier.
3. SYSCLK must be at least 32 kHz to enable debugging.
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Rev. 1.1