C8051F352 Datasheet, PDF (158/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
SFR Definition 19.1. SMB0CF: SMBus Clock/Configuration
R/W
R/W
ENSMB INH
Bit7
Bit6
R
BUSY
Bit5
R/W
R/W
EXTHOLD SMBTOE
Bit4
Bit3
R/W
SMBFTE
Bit2
R/W
R/W
Reset Value
SMBCS1 SMBCS0 00000000
Bit1
Bit0
SFR Address: 0xC1
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bits1–0:
ENSMB: SMBus Enable.
This bit enables/disables the SMBus interface. When enabled, the interface constantly mon-
itors the SDA and SCL pins.
0: SMBus interface disabled.
1: SMBus interface enabled.
INH: SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave events
occur. This effectively removes the SMBus slave from the bus. Master Mode interrupts are
not affected.
0: SMBus Slave Mode enabled.
1: SMBus Slave Mode inhibited.
BUSY: SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0
when a STOP or free-timeout is sensed.
EXTHOLD: SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to Table 19.2.
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
SMBTOE: SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces Timer 3 to
reload while SCL is high and allows Timer 3 to count when SCL goes low. If Timer 3 is con-
figured in split mode (T3SPLIT is set), only the high byte of Timer 3 is held in reload while
SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms, and the
Timer 3 interrupt service routine should reset SMBus communication.
SMBFTE: SMBus Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for
more than 10 SMBus clock source periods.
SMBCS1–SMBCS0: SMBus Clock Source Selection.
These two bits select the SMBus clock source, which is used to generate the SMBus bit
rate. The selected device should be configured according to Equation 19.1.
SMBCS1
0
0
1
1
SMBCS0
0
1
0
1
SMBus Clock Source
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
158
Rev. 1.1