C8051F352 Datasheet, PDF (62/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
Table 5.3. ADC0 Electrical Characteristics (Continued)
V_DD = AV+ = 3.0 V, VREF = 2.5 V External, PGA Gain = 1, MDCLK = 2.4576 MHz,
Decimation Ratio = 1920, –40 to +85 °C unless otherwise noted.
Parameter
Power Specifications
AV+ Supply Current to ADC0
AV+ Supply Current to Input Buffers
(Each Enabled Buffer)
Power Supply Rejection
Conditions
Min
Typ
—
230
—
90
80
—
Max Units
650
µA
125
µA
—
dB
Table 5.4. ADC0 SINC3 Filter Typical RMS Noise (µV)
Decimation Output Word
PGA Gain Setting
Ratio
Rate*
1
2
4
8
16
32
1920
10 Hz
2.38 1.23 0.68 0.41 0.24 0.16
768
25 Hz
3.90 2.04 1.14 0.68 0.44 0.33
640
30 Hz
4.50 2.39 1.31 0.81 0.54 0.42
384
50 Hz
6.00 3.21 1.86 1.20 0.86 0.73
320
60 Hz
7.26 3.96 2.32 1.51 1.11 0.97
192
100 Hz
13.1 7.11 4.24 2.85 2.16 1.91
80
240 Hz
93.2 47.7 24.8 13.9 9.34 7.61
40
480 Hz
537 267 135 69.5 38.8 25.7
20
960 Hz
2974 1586 771 379 196 108
*Note: Output Word Rate assuming Modulator Clock frequency = 2.4576 MHz
(sampling clock frequency = 19.2 kHz)
64
0.12
0.28
0.36
0.66
0.89
1.79
6.97
20.9
70.0
128
0.11
0.27
0.36
0.66
0.89
1.77
6.67
18.9
45.4
62
Rev. 1.1