C8051F352 Datasheet, PDF (11/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
List of Tables
1. System Overview
Table 1.1. Product Selection Guide ......................................................................... 18
2. Absolute Maximum Ratings
3. Global DC Electrical Characteristics
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F350/1/2/3 ................................................. 31
Table 4.2. LQFP-32 Package Dimensions .............................................................. 36
Table 4.3. QFN-28 Package Dimensions ................................................................ 37
5. 24 or 16-Bit Analog to Digital Converter (ADC0)
Table 5.1. ADC0 Unipolar Output Word Coding (AD0POL = 0) .............................. 47
Table 5.2. ADC0 Bipolar Output Word Coding (AD0POL = 1) ................................ 47
Table 5.3. ADC0 SINC3 Filter Typical RMS Noise (µV) .......................................... 62
Table 5.4. ADC0 SINC3 Filter Effective Resolution
in Unipolar Mode (bits) ......................................................................... 63
Table 5.5. ADC0 SINC3 Filter Flicker-Free (Noise-Free) Resolution
in Unipolar Mode (bits) ......................................................................... 63
Table 5.6. ADC0 Fast Filter Typical RMS Noise (µV) ............................................. 64
Table 5.7. ADC0 Fast Filter Effective Resolution¹ in Unipolar Mode (bits) ............. 64
Table 5.8. ADC0 Fast Filter Flicker-Free (Noise-Free) Resolution
in Unipolar Mode (bits) ......................................................................... 65
6. 8-Bit Current Mode DACS (IDA0 and IDA1)
7. Voltage Reference
8. Temperature Sensor
9. Comparator0
10. CIP-51 Microcontroller
Table 10.1. CIP-51 Instruction Set Summary .......................................................... 89
11. Memory Organization and SFRs
Table 11.1. Special Function Register (SFR) Memory Map .................................. 101
Table 11.2. Special Function Registers ................................................................. 102
12. Interrupt Handler
Table 12.1. Interrupt Summary .............................................................................. 106
13. Prefetch Engine
14. Reset Sources
15. Flash Memory
16. External RAM
17. Oscillators
18. Port Input/Output
19. SMBus
Table 19.1. SMBus Clock Source Selection .......................................................... 156
Table 19.2. Minimum SDA Setup and Hold Times ................................................ 157
Table 19.3. Sources for Hardware Changes to SMB0CN ..................................... 161
Table 19.4. SMBus Status Decoding ..................................................................... 167
20. UART0
Rev. 1.1
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