C8051F352 Datasheet, PDF (129/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
17. Oscillators
C8051F350/1/2/3 devices include a programmable internal oscillator, an external oscillator drive circuit,
and a clock multiplier. The internal oscillator can be enabled/disabled and calibrated using the OSCICN
and OSCICL registers, as shown in Figure 17.1. The system clock (SYSCLK) can be derived from the
internal oscillator, external oscillator circuit, or the clock multiplier. The clock multiplier can produce three
possible outputs: Internal Oscillator x 2, External Oscillator x 2, or External Oscillator x 4. Oscillator electri-
cal specifications are given in Table 17.1 on page 136.
Option 2
VDD
XTAL2
Option 3
XTAL2
Option 1
XTAL1
10MΩ
XTAL2
Option 4
XTAL2
OSCICL
OSCICN
CLKSEL
EN
Programmable ^IOSC
Internal Clock
n
Generator
Input
Circuit
EXOSC
OSC
IOSC/2
EXOSC
x4
EXOSC / 2
Clock Multiplier
SYSCLK
OSCXCN
CLKMUL
Figure 17.1. Oscillator Diagram
17.1. Programmable Internal Oscillator
All C8051F350/1/2/3 devices include a programmable internal oscillator that defaults as the system clock
after a system reset. The internal oscillator period can be programmed via the OSCICL register, shown in
SFR Definition 17.2. On C8051F350/1/2/3 devices, OSCICL is factory calibrated to obtain a 24.5 MHz fre-
quency.
Electrical specifications for the precision internal oscillator are given in Table 17.1 on page 136. Note that
the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as
defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset.
Rev. 1.1
129