C8051F352 Datasheet, PDF (56/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
SFR Definition 5.13. ADC0CGH: ADC0 Gain Calibration Register High Byte
R/W
GCAL23
Bit7
R/W
GCAL22
Bit6
R/W
GCAL21
Bit5
R/W
GCAL20
Bit4
R/W
GCAL19
Bit3
R/W
GCAL18
Bit2
R/W
R/W
Reset Value
GCAL17 GCAL16 Variable
Bit1
Bit0 10000000
SFR Address: 0xAD
Bits 7–0: GCAL[23:16]: ADC0 Gain Calibration Register High Byte.
This register contains the high byte of the 24-bit ADC Gain Calibration Value.
SFR Definition 5.14. ADC0CGM: ADC0 Gain Calibration Register Middle Byte
R/W
GCAL15
Bit7
R/W
GCAL14
Bit6
R/W
GCAL13
Bit5
R/W
GCAL12
Bit4
R/W
GCAL11
Bit3
R/W
GCAL10
Bit2
R/W
GCAL9
Bit1
R/W
Reset Value
GCAL8 00000000
Bit0
SFR Address: 0xAC
Bits 7–0: GCAL[15:8]: ADC0 Gain Calibration Register Middle Byte.
This register contains the middle byte of the 24-bit ADC Gain Calibration Value.
SFR Definition 5.15. ADC0CGL: ADC0 Gain Calibration Register Low Byte
R/W
GCAL7
Bit7
R/W
GCAL6
Bit6
R/W
GCAL5
Bit5
R/W
GCAL4
Bit4
R/W
GCAL3
Bit3
R/W
GCAL2
Bit2
R/W
GCAL1
Bit1
R/W
Reset Value
GCAL0 00000000
Bit0
SFR Address: 0xAB
Bits 7–0: GCAL[7:0]: ADC0 Gain Calibration Register Low Byte.
This register contains the low byte of the 24-bit ADC Gain Calibration Value.
56
Rev. 1.1