C8051F352 Datasheet, PDF (208/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
22.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 22.7. TMR3RLL holds the reload value for TMR3L; TMR3RLH
holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select either SYSCLK or
the clock defined by the Timer 3 External Clock Select bit (T3XCLK in TMR3CN), as follows:
T3MH
0
0
1
T3XCLK
0
1
X
TMR3H Clock
Source
SYSCLK / 12
External Clock / 8
SYSCLK
T3ML
0
0
1
T3XCLK
0
1
X
TMR3L Clock
Source
SYSCLK / 12
External Clock / 8
SYSCLK
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled (IE.5), an interrupt is generated each time
TMR3H overflows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is gener-
ated each time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the
TF3H and TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags
are not cleared by hardware and must be manually cleared by software.
T3XCLK
SYSCLK / 12
0
External Clock / 8
1
CKCON
TTTTTTSS
3 3 2 2 1 0 CC
MMMMMMA A
HLHL 10
0
TR3
1
SYSCLK
1
0
Reload
TMR3RLH
TCLK
TMR3H
TMR3RLL ^Reload
TCLK _TMR3L
TF3H
TF3L
TF3LEN
T3SPLIT
TR3
T3XCLK
Figure 22.7. Timer 3 8-Bit Mode Block Diagram
Interrupt
208
Rev. 1.1