C8051F352 Datasheet, PDF (73/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
7. Voltage Reference
There are two voltage reference options for the C8051F350/1/2/3 ADCs: the internal 2.5 V reference volt-
age, or an external reference voltage (see Figure 7.1). The AD0VREF bit in the ADC0CF register selects
the reference source.
The internal voltage reference circuit consists of a 1.25 V, temperature stable bandgap voltage reference
generator and a gain-of-two output buffer amplifier, to produce a 2.5 V voltage reference. When the inter-
nal voltage reference is used, it is driven out on the VREF+ pin. In this configuration, the VREF– must be
connected to the AGND pin external to the device. See Section “24. Revision Specific Behavior’ on
page 227 for more information. The internal voltage reference is enabled by setting the AD0EN bit in regis-
ter ADC0MD to ‘1’ and clearing the AD0VREF bit in register ADC0CF to ‘0’ (See Section “5. 24 or 16-Bit
Analog to Digital Converter (ADC0)’ on page 41). Electrical specifications for the internal voltage reference
and bias generators are given in Table 7.1.
The internal oscillator bias generator is automatically enabled whenever the internal oscillator is enabled.
For power requirement characterization, the BIASE bit in register REF0CN can also be used to enable the
internal oscillator bias generator, when the oscillator itself is not enabled. Likewise, the REFBE bit in regis-
ter REF0CN can be used to enable the internal bandgap generator, which is used by the ADC, the IDACs,
the Clock Multiplier, and the internal Voltage Reference. The internal reference bias generator is automati-
cally enabled whenever a peripheral requires it. See SFR Definition 7.1 for the REF0CN register descrip-
tion.
IOSCEN
BIASE
REFBE
Bypass
Capacitors
(Recommended)
External
Voltage
+
Reference
(Optional)
AD0EN
AD0VREF
VREF+
VREF–
AD0EN
IDA0EN
IDA1EN
MULEN
Internal
EN _{Oscillator Bias}
Generator
EN
Internal
Reference
Bias Generator
EN
2.5 V
Reference
Buffer
VREF to ADC
Figure 7.1. Reference Circuitry Block Diagram
To Internal
Oscillator
To ADC, IDACs,
Clock Multiplier
Rev. 1.1
73