C8051F352 Datasheet, PDF (140/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
P0
P1
P2
SF Signals
x1 x2
CNVSTR
IDA0 IDA1
PIN I/O
01234567012345670
TX0
RX0
CP0A
CP0
SCK
MISO
MOSI
NSS*
(*4-Wire SPI Only)
SDA
SCL
/SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0011000000000000
P0SKIP[0:7]
P1SKIP[0:7]
SF Signals
Port pin potentially assignable to peripheral
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the CrossBar must be
manually configured to skip their corresponding port pins.
Figure 18.4. Crossbar Priority Decoder with Crystal Pins Skipped
Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and
SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX).
UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART
RX0 is always assigned to P0.5. Comparator outputs are also fixed: CP0A will appear only on P1.4, CP0
will appear only on P1.5. Standard Port I/Os appear contiguously after the prioritized functions have been
assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the
NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not
be routed to a Port pin.
140
Rev. 1.1