C8051F352 Datasheet, PDF (50/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
SFR Definition 5.3. ADC0MD: ADC0 Mode
R/W
AD0EN
Bit7
R
R/W
R/W
R
— Reserved Reserved —
Bit6
Bit5
Bit4
Bit3
R/W
R/W
R/W
Reset Value
AD0SM
00000000
Bit2
Bit1
Bit0
SFR Address: 0xF3
Bit 7: AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC is in low-power shutdown.
1: ADC0 Enabled. ADC is active and ready to perform calibrations or conversions.
Note: Disabling the ADC automatically resets the AD0SM bits back to the "Idle" state.
Bit 6: Unused: Read = 0b, Write = don’t care.
Bits 5–4: RESERVED: Must Write to 00b.
Bit 3: Unused: Read = 0b, Write = don’t care.
Bits 2–0: AD0SM: ADC0 System Mode Select.
These bits define the operating mode for the ADC. They are used to initiate all ADC conver-
sion and calibration cycles.
000: Idle
001: Full Internal Calibration (offset and gain).
010: Single Conversion.
011: Continuous Conversion.
100: Internal Offset Calibration.
101: Internal Gain Calibration.
110: System Offset Calibration.
111: System Gain Calibration.
Note: Any system mode change by the user during a conversion or calibration will
terminate the operation, and corrupt the result. To write to many of the other ADC reg-
isters, the AD0SM bits must be set to IDLE mode (000b).
Note: During an ADC conversion or calibration, the AD0SM bits may return intermedi-
ate values if they are read. It is not recommended to use these bits as indicator of the
ADC status. Only the ADC0STA register should be used as indicator of the ADC sta-
tus.
50
Rev. 1.1