C8051F352 Datasheet, PDF (181/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
21. Serial Peripheral Interface (SPI0)
The Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus.
SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple mas-
ters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select
SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding conten-
tion on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be
configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general pur-
pose port I/O pins can be used to select multiple slave devices in master mode.
SPI0CKR
SFR Bus
SPI0CFG
SPI0CN
SYSCLK
Clock Divide
Logic
SPI CONTROL LOGIC
Data Path
Control
Pin Interface
Control
SPI IRQ
Tx Data
MOSI
C
SPI0DAT
Transmit Data Buffer
SCK ^R
O
Shift Register
76543210
Pin
S
Control
Logic
Rx Data
MISO
S
B
A
R
Receive Data Buffer
NSS
Write
SPI0DAT
Read
SPI0DAT
SFR Bus
Figure 21.1. SPI Block Diagram
Port I/O
Rev. 1.1
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