C8051F352 Datasheet, PDF (180/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
Table 20.5. Timer Settings for Standard Baud Rates
Using an External 11.0592 MHz Oscillator
Target
Baud Rate
(bps)
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
Frequency: 11.0592 MHz
Baud Rate Oscilla- Timer Clock SCA1–SCA0 T1M* Timer 1
% Error tor Divide Source
(pre-scale
Reload
Factor
select)*
Value (hex)
0.00%
48
SYSCLK
XX
1
0xE8
0.00%
96
SYSCLK
XX
1
0xD0
0.00%
192
SYSCLK
XX
1
0xA0
0.00%
384
SYSCLK
XX
1
0x40
0.00%
768 SYSCLK / 12
00
0
0xE0
0.00%
1152 SYSCLK / 12
00
0
0xD0
0.00%
4608 SYSCLK / 12
00
0
0x40
0.00%
9216 SYSCLK / 48
10
0
0xA0
0.00%
48
EXTCLK / 8
11
0
0xFD
0.00%
96
EXTCLK / 8
11
0
0xFA
0.00%
192 EXTCLK / 8
11
0
0xF4
0.00%
384 EXTCLK / 8
11
0
0xE8
0.00%
768 EXTCLK / 8
11
0
0xD0
0.00%
1152 EXTCLK / 8
11
0
0xB8
X = Don’t care
*Note: SCA1–SCA0 and T1M bit definitions can be found in Section 22.1.
Table 20.6. Timer Settings for Standard Baud Rates
Using an External 3.6864 MHz Oscillator
Target
Baud Rate
(bps)
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
Frequency: 3.6864 MHz
Baud
Oscilla- Timer Clock SCA1–SCA0 T1M* Timer 1
Rate% tor Divide Source
(pre-scale
Reload
Error
Factor
select)*
Value (hex)
0.00%
16
SYSCLK
XX
1
0xF8
0.00%
32
SYSCLK
XX
1
0xF0
0.00%
64
SYSCLK
XX
1
0xE0
0.00%
128
SYSCLK
XX
1
0xC0
0.00%
256
SYSCLK
XX
1
0x80
0.00%
384
SYSCLK
XX
1
0x40
0.00%
1536 SYSCLK / 12
00
0
0xC0
0.00%
3072 SYSCLK / 12
00
0
0x80
0.00%
16
EXTCLK / 8
11
0
0xFF
0.00%
32
EXTCLK / 8
11
0
0xFE
0.00%
64
EXTCLK / 8
11
0
0xFC
0.00%
128
EXTCLK / 8
11
0
0xF8
0.00%
256
EXTCLK / 8
11
0
0xF0
0.00%
384
EXTCLK / 8
11
0
0xE8
X = Don’t care
*Note: SCA1–SCA0 and T1M bit definitions can be found in Section 22.1.
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Rev. 1.1