C8051F352 Datasheet, PDF (198/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
22.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The
counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0,
GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0
register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled
using the Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls
the Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates for the SMBus and UART. While Timer 0 is oper-
ating in Mode 3, Timer 1 run control is handled through its mode settings. To run Timer 1 while Timer 0 is in
Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1, configure it for Mode 3.
Pre-scaled Clock
SYSCLK
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL
10
TMOD
GCT TGC T T
A / 11A / 00
T T MM T T MM
E1 1 0E0 1 0
1
0
0
TR1
1
0
1
T0
Crossbar
GATE0
TR0
TH0
(8 bits)
TL0
(8 bits)
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Interrupt
/INT0
IN0PL _XOR
Figure 22.3. T0 Mode 3 Block Diagram
198
Rev. 1.1