C8051F352 Datasheet, PDF (149/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
SFR Definition 18.11. P2: Port2
R
R
R
R
R
R
R
R/W
Reset Value
—
—
—
—
—
—
—
P2.0 00000001
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address: 0xA0
Bits7–1:
Bit0:
Unused. Read = 0000000b. Write = don’t care.
P2.0
Write - Output appears on I/O pins per Crossbar Registers.
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P2MDOUT.n bit = 0).
Read - Directly reads Port pin.
0: P2.n pin is logic low.
1: P2.n pin is logic high.
SFR Definition 18.12. P2MDOUT: Port2 Output Mode
R
R
R
R
R
R
—
—
—
—
—
—
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bits7–1:
Bit0:
Unused. Read = 0000000b. Write = don’t care.
Output Configuration Bit for P2.0.
0: P2.0 Output is open-drain.
1: P2.0 Output is push-pull.
R
R/W
Reset Value
—
00000000
Bit1
Bit0
SFR Address: 0xA6
Rev. 1.1
149