C8051F352 Datasheet, PDF (147/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
SFR Definition 18.7. P1: Port1
R/W
P1.7
Bit7
R/W
P1.6
Bit6
R/W
P1.5
Bit5
R/W
P1.4
Bit4
R/W
P1.3
Bit3
R/W
P1.2
Bit2
R/W
P1.1
Bit1
R/W
Reset Value
P1.0 11111111
Bit0
Bit
Addressable
SFR Address: 0x90
Bits7–0:
P1.[7:0]
Write - Output appears on I/O pins per Crossbar Registers.
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0).
Read - Always reads ‘0’ if selected as analog input in register P1MDIN. Directly reads Port
pin when configured as digital input.
0: P1.n pin is logic low.
1: P1.n pin is logic high.
SFR Definition 18.8. P1MDIN: Port1 Input Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xF2
Bits7–0:
Analog Input Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured as analog inputs have their weak pull-up, digital driver, and digital
receiver disabled.
0: Corresponding P1.n pin is configured as an analog input.
1: Corresponding P1.n pin is not configured as an analog input.
Rev. 1.1
147