C8051F352 Datasheet, PDF (130/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
SFR Definition 17.1. OSCICN: Internal Oscillator Control
R/W
R
R
R
R
R
R/W
R/W
Reset Value
IOSCEN IFRDY
—
—
—
—
IFCN1 IFCN0 11000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xB2
Bit7:
Bit6:
Bits5–2:
Bits1–0:
IOSCEN: Internal Oscillator Enable Bit.
0: Internal Oscillator Disabled.
1: Internal Oscillator Enabled.
IFRDY: Internal Oscillator Frequency Ready Flag.
0: Internal Oscillator is not running at programmed frequency.
1: Internal Oscillator is running at programmed frequency.
UNUSED. Read = 0000b, Write = don't care.
IFCN1–0: Internal Oscillator Frequency Control Bits.
00: SYSCLK derived from Internal Oscillator divided by 8.
01: SYSCLK derived from Internal Oscillator divided by 4.
10: SYSCLK derived from Internal Oscillator divided by 2.
11: SYSCLK derived from Internal Oscillator divided by 1.
SFR Definition 17.2. OSCICL: Internal Oscillator Calibration
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Variable
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xB3
Bit7: UNUSED. Read = 0. Write = don’t care.
Bits 6–0: OSCICL: Internal Oscillator Calibration Register.
This register determines the internal oscillator period. On C8051F350/1/2/3 devices, the
reset value is factory calibrated to generate an internal oscillator frequency of 24.5 MHz.
130
Rev. 1.1