C8051F352 Datasheet, PDF (143/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
SFR Definition 18.2. XBR1: Port I/O Crossbar Register 1
R/W
R/W
R/W
R/W
R/W
R
WEAKPUD XBARE T1E
T0E
ECIE
—
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
R/W
R/W
Reset Value
PCA0ME
00000000
Bit1
Bit0
SFR Address: 0xE2
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bits1–0:
WEAKPUD: Port I/O Weak Pull-up Disable.
0: Weak Pull-ups enabled (except for Ports whose I/O are configured as analog input).
1: Weak Pull-ups disabled.
XBARE: Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
T1E: T1 Enable
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
T0E: T0 Enable
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
ECIE: PCA0 External Counter Input Enable
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
Unused. Read = 0b. Write = don’t care.
PCA0ME: PCA Module I/O Enable Bits.
00: All PCA I/O unavailable at Port pins.
01: CEX0 routed to Port pin.
10: CEX0, CEX1 routed to Port pins.
11: CEX0, CEX1, CEX2 routed to Port pins.
Rev. 1.1
143