C8051F352 Datasheet, PDF (51/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
SFR Definition 5.4. ADC0CLK: ADC0 Modulator Clock Divisor
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
ADC0CLK
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xF7
Bits 7–0: ADC0CLK: ADC0 Modulator Clock Divisor.
This register establishes the Modulator Clock (MDCLK), by dividing down the system clock
(SYSCLK). The input signal is sampled by the modulator at a frequency of MDCLK / 128.
For optimal performance, the divider should be chosen such that the modulator clock is
equal to 2.4576 MHz (modulator sampling rate = 19.2 kHz).
The system clock is divided according to the equation:
MDCLK = SYSCLK / (ADC0CLK + 1)
Note: The Modulator Sampling Rate is not the ADC Output Word Rate. See Section 5.1.4 for
details.
SFR Definition 5.5. ADC0DECH: ADC0 Decimation Ratio Register High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
—
—
—
—
—
DECI10 DECI9 DECI8 00000111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x9B
Bits 7–3: Unused: Read = 00000b, Write = don’t care.
Bits 2–0: DECI[10:8]: ADC0 Decimation Ratio Register, Bits 10–8.
This register contains the high bits of the 11-bit ADC Decimation Ratio. The decimation ratio
determines the output word rate of ADC0, based on the Modulator Clock (MDCLK). See the
ADC0DECL register description for more information.
This SFR can only be modified when ADC0 is in IDLE mode.
Rev. 1.1
51