C8051F352 Datasheet, PDF (43/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
Bypass Buffer
High Buffer+
AIN+
Channel
Low Buffer+
High Buffer-
To PGA
AD0BPHE
AD0BPLE
AD0BPS1
AD0BPS0
AD0BNHE
AD0BNLE
AD0BNS1
AD0BNS0
AIN-
Channel
Low Buffer-
To PGA
Bypass Buffer
Figure 5.2. ADC0 Buffer Control
5.1.3. Modulator Clock
The ADC0CLK register (SFR Definition 5.4) holds the Modulator Clock (MDCLK) divisor value. The modu-
lator clock determines the switching frequency for the ADC sampling capacitors. Optimal performance will
be achieved when the MDCLK frequency is equal to 2.4576 MHz. The modulator samples the input at a
rate of MDCLK / 128.
5.1.4. Decimation Ratio
The decimation ratio of the ADC filters is selected by the DECI[10:0] bits in the ADC0DECH and
ADC0DECL registers (SFR Definition 5.5 and SFR Definition 5.6, respectively). The decimation ratio is
equal to 1 + DECI[10:0]. The decimation ratio determines how many modulator samples are used to gen-
erate a single output word. The ADC output word rate is equal to the modulator sampling rate divided by
the decimation ratio. For more information on how the ADC output word rate is derived, see SFR Definition
5.4 and SFR Definition 5.6. Higher decimation ratios will produce lower-noise results over a longer conver-
sion period. The minimum decimation ratio is 20. When using the fast filter output, the decimation ratio
must be set to a multiple of 8.
Rev. 1.1
43