C8051F352 Datasheet, PDF (126/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
SFR Definition 15.3. FLSCL: Flash Scale
R/W
R/W
R/W
Reserved Reserved Reserved
Bit7
Bit6
Bit5
R/W
FLRT
Bit4
R/W
R/W
R/W
R/W
Reset Value
Reserved Reserved Reserved Reserved 00000000
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xB6
Bits7–5:
Bit 4:
Bits3–0:
RESERVED. Read = 000b. Must Write 000b.
FLRT: Flash Read Time.
This bit should be programmed to the smallest allowed value, according to the system clock
speed.
0: SYSCLK < 25 MHz.
1: SYSCLK < 50 MHz.
RESERVED. Read = 0000b. Must Write 0000b.
Table 15.1. Flash Electrical Characteristics
V_DD = 2.7 to 3.6 V; –40 to +85 ºC unless otherwise specified.
Parameter
Flash Size
Endurance
Erase Cycle Time
Write Cycle Time
Conditions
C8051F350/1/2/3
50 MHz System Clock
50 MHz System Clock
Min
8192*
20 k
10
40
Typ
—
100 k
15
55
Max
—
—
20
70
Units
bytes
Erase/Write
ms
µs
*Note: 512 bytes at addresses 0x1E00 to 0x1FFF are reserved.
126
Rev. 1.1