C8051F352 Datasheet, PDF (69/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
SFR Definition 6.1. IDA0CN: IDA0 Control
R/W
R/W
R/W
R/W
R/W
R
IDA0EN
IDA0CM
IDA0CSC —
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
R/W
R/W
Reset Value
IDA0OMD
01110000
Bit1
Bit0
SFR Address: 0xB9
Bit 7: IDA0EN: IDA0 Enable.
0: IDA0 Disabled.
1: IDA0 Enabled.
Bits 6–4: IDA0CM[2:0]: IDA0 Update Source Select bits.
000: DAC output updates on Timer 0 overflow.
001: DAC output updates on Timer 1 overflow.
010: DAC output updates on Timer 2 overflow.
011: DAC output updates on Timer 3 overflow.
100: DAC output updates on rising edge of CNVSTR.
101: DAC output updates on falling edge of CNVSTR.
110: DAC output updates on any edge of CNVSTR.
111: DAC output updates on write to IDA0.
Bit 3: IDA0CSC: IDA0 Constant Supply Current.
0: Current draw on V_DD is dependent on IDA0 Output Word.
1: Current draw on V_DD is independent of IDA0 Output Word.
Bit 2: Unused. Read = 0b, Write = Don’t Care.
Bits 1:0: IDA0OMD[1:0]: IDA0 Output Mode Select bits.
00: 0.25 mA full-scale output current.
01: 0.5 mA full-scale output current.
10: 1.0 mA full-scale output current.
11: 2.0 mA full-scale output current.
SFR Definition 6.2. IDA0: IDA0 Data Word
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x96
Bits 7–0: IDA0 Data Word Bits.
Bits 7–0 hold the 8-bit IDA0 Data Word.
Rev. 1.1
69