C8051F352 Datasheet, PDF (46/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
5.3. Performing Conversions
The ADC offers two conversion modes: Single Conversion, and Continuous Conversion. In single conver-
sion mode, a single conversion result is produced for each of the filters (SINC3 and Fast). In continuous
conversion mode, the ADC will perform back-to-back conversions until the ADC mode is changed. Proce-
dures for single and continuous conversion modes are detailed in the sections below.
5.3.1. Single Conversions
A single conversion is initiated by writing the ADC System Mode bits (AD0SM) to the “Single Conversion”
option. Single conversion mode instructs the ADC to gather enough information to produce a result for the
filter that is selected by the AD0ISEL bit. During the conversion, the AD0BUSY flag will be set to ‘1’. The
Fast filter results will be available after one period of the ADC’s conversion cycle (determined by the mod-
ulator clock and the decimation ratio). The SINC3 filter results will be available after three periods of the
ADC’s conversion cycle. The AD0ISEL bit in register ADC0CF determines when the end-of-conversion
interrupt will occur, and return the ADC to Idle mode. If the AD0ISEL bit is set to ‘1’, the AD0INT bit will be
set to ‘1’ when the Fast filter results are available. If the AD0ISEL bit is cleared to ‘0’, the AD0INT bit will be
set to ‘1’ when the SINC3 filter results are available. The AD0SM bits will return to idle mode and the
AD0BUSY bit will be cleared to ‘0’ when the selected filter is finished. When using the SINC3 filter, a valid
result will also be output by the Fast filter. When using the Fast filter in single-conversion mode, the SINC3
filter results will not be accurate.
5.3.2. Continuous Conversions
Continuous conversions are initiated by writing the ADC System Mode bits (AD0SM) to the “Continuous
Conversion” option. In continous conversion mode, the ADC will start a new conversion as soon as each
conversion is completed. During the conversions, the AD0BUSY flag will be set to ‘1’. The Fast filter results
will be available after one period of the ADC’s conversion cycle, and on every conversion cycle thereafter
(determined by the modulator clock and the decimation ratio). The first SINC3 filter result will be available
after three periods of the ADC’s conversion cycle, and subsequent SINC3 conversion results will be avail-
able at the end of every conversion cycle thereafter. The AD0ISEL bit in register ADC0CF determines
when the end-of-conversion interrupts will occur. If the AD0ISEL bit is cleared to ‘0’, the AD0INT bit will be
set to ‘1’ when SINC3 filter results are available. If the AD0ISEL bit is set to ‘1’, the AD0INT bit will be set to
‘1’ when Fast filter results are available. Regardless of the setting of the AD0ISEL bit, both filters will
update their results registers when new results are available. To stop conversions and exit from continuous
conversion mode, the AD0SM bits should be written to Idle mode.
5.3.3. ADC Output
The ADC’s two filters each have their own output data registers. The SINC3 filter results are stored in the
ADC0H, ADC0M, and ADC0L registers, while the Fast filter results are stored in the ADC0FH, ADC0FM,
and ADC0FL registers. The ADC output can be configured for Unipolar or Bipolar mode using the AD0POL
bit in register ADC0CN. Decoding of the ADC output words are shown in Table 5.1 and Table 5.2. The
SINC3 filter uses information from the past three conversion cycles to produce an ADC output. The Fast fil-
ter uses information from only the current conversion cycle to produce an ADC output. The fast filter reacts
more quickly to changes on the analog input, while the SINC3 filter produces lower-noise results.
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