C8051F352 Datasheet, PDF (110/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
SFR Definition 12.4. EIP1: Extended Interrupt Priority 1
R/W
PT3
Bit7
R/W
Reserved
Bit6
R/W
PCP0
Bit5
R/W
PPCA0
Bit4
R/W
PADC0
Bit3
R/W
R/W
R/W
Reset Value
Reserved Reserved PSMB0 00000000
Bit2
Bit1
Bit0
SFR Address: 0xF6
Bit 7: PT3: Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
Bit 6: RESERVED. Read = 0. Must Write 0.
Bit 5: PCP0: Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
Bit 4: PPCA0: Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
Bit 3: PADC0 ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
Bits 2–1: RESERVED. Read = 00. Must Write 00.
Bit 0: PSMB0: SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
110
Rev. 1.1