C8051F352 Datasheet, PDF (19/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
VDD
GND
AV+
AGND
/RST/C2CK
VREF+
VREF–
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
Digital Power
Analog
Power
C2D
Debug HW
POR
Brown-
Out
XTAL1
XTAL2
External
Oscillator
Circuit
24.5 MHz 2%
Internal
Oscillator
Clock
Multiplier
8
0
5 ^Reset
1
8 kB
FLASH
256 byte
SRAM
512 byte
XRAM
C
o ^{SFR Bus}
r ^System
Clock
e
VREF
Offset
DAC
A
+
M
Buffer
PGA
+
U
X
24-bit
ADC0
Temp
Sensor
Port 0
Latch
UART
Timer 0,
1, 2, 3
3-Chnl
PCA/
WDT
SMBus
SPI Bus
Port 1
Latch
8-bit
IDAC0
8-bit
IDAC1
Port 2
Latch
P
0
D
r
v
X
B
A
R
CP0
CP0A
CP0+
+
- ^CP0-
P
1
D
r
v
C2D
P0.0
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4/CP0A
P1.5/CP0
P1.6/IDAC0
P1.7/IDAC1
P2.0/C2D
Figure 1.1. C8051F350 Block Diagram
VDD
GND
AV+
AGND
/RST/C2CK
VREF+
VREF–
AIN0
AIN1
AIN2
AIN3
Digital Power
Analog
Power
C2D
Debug HW
POR
Brown-
Out
XTAL1
XTAL2
External
Oscillator
Circuit
24.5 MHz 2%
Internal
Oscillator
Clock
Multiplier
8
0
5 ^Reset
1
8 kB
FLASH
256 byte
SRAM
512 byte
XRAM
C
o ^{SFR Bus}
r ^System
Clock
e
VREF
A
M
AIN4
U
AIN5
X
AIN6
AIN7
Buffer
Offset
DAC
+
PGA
+
Temp
Sensor
24-bit
ADC0
Port 0
Latch
UART
Timer 0,
1, 2, 3
3-Chnl
PCA/
WDT
SMBus
SPI Bus
Port 1
Latch
8-bit
IDAC0
8-bit
IDAC1
Port 2
Latch
P
0
D
r
v
X
B
A
R
CP0
CP0A
CP0+
+
- ^CP0-
AIN4-7
P
1
D
r
v
C2D
P0.0
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
P1.0/AIN4
P1.1/AIN5
P1.2/AIN6
P1.3/AIN7
P1.4/CP0A
P1.5/CP0
P1.6/IDAC0
P1.7/IDAC1
P2.0/C2D
Figure 1.2. C8051F351 Block Diagram
Rev. 1.1
19