C8051F352 Datasheet, PDF (53/234 Pages) Silicon Laboratories – 8 k ISP Flash MCU Family

C8051F350/1/2/3
SFR Definition 5.8. ADC0BUF: ADC0 Input Buffer Control
R/W
R/W
AD0BPHE AD0BPLE
Bit7
Bit6
R/W
R/W
AD0BPS
Bit5
Bit4
R/W
R/W
AD0BNHE AD0BNLE
Bit3
Bit2
R/W
R/W
Reset Value
AD0BNS
00000000
Bit1
Bit0
SFR Address: 0xBD
Bit 7: AD0BPHE: Positive Channel High Buffer Enable.
0: Positive Channel High Input Buffer Disabled.
1: Positive Channel High Input Buffer Enabled.
Bit 6: AD0BPLE: Positive Channel Low Enable.
0: Positive Channel Low Input Buffer Disabled.
1: Positive Channel Low Input Buffer Enabled.
Bits 5–4: AD0BPS: Positive Channel Input Selection.
00 = Bypass Input Buffer (default).
01 = Select Low Input Buffer Range.
10 = Select High Input Buffer Range.
11 = Reserved.
Bit 3: AD0BNHE: Negative Channel High Buffer Enable.
0: Negative Channel High Input Buffer Disabled.
1: Negative Channel High Input Buffer Enabled.
Bit 2: AD0BNLE: Negative Channel Low Enable.
0: Negative Channel Low Input Buffer Disabled.
1: Negative Channel Low Input Buffer Enabled.
Bits 1–0: AD0BNS: Negative Channel Input Selection.
00 = Bypass Input Buffer (default).
01 = Select Low Input Buffer Range.
10 = Select High Input Buffer Range.
11 = Reserved.
This SFR can only be modified when ADC0 is in IDLE mode.
Rev. 1.1
53