K5N1229ACD-BQ12 Datasheet, PDF (97/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
CLK
CRE
tSP tHD
ADV
A[22:16]
(Except A[19:18])
tSP tHD
tSP tHD
ADDRESS
ADDRESS
A[19:18]
CS
OE
ADDRESS
tCSP
tABA
tBOE
tCBPH³
ADDRESS
tHZ
tOHZ
LB/UB
WAIT _High-Z
tSP
tOLZ
tKW
tHD
A/DQ[15:0]
ADDRESS
tACLK
CR
Valid
High-Z
ADDRESS
DATA
VALID
Latch Control Register Address
tKOH
Don’t Care
Undefined
Figure 7. Register READ, Synchronous Mode Followed by READ ARRAY Operation
NOTE :
1) Non-default BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code two (three clocks);
WAIT active LOW; WAIT asserted during delay.
2) A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.
3) CS must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles caused by refresh collisions
require a corresponding number of additional CS LOW cycles.
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