K5N1229ACD-BQ12 Datasheet, PDF (101/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of four, eight, sixteen, or thirty-two
words. The initial latency for READ operations can be configured as fixed or variable (WRITE operations always use fixed latency). Variable latency
allows minimum latency at high clock frequencies, but the controller must monitor WAIT to detect any conflict with refresh cycles. Fixed latency outputs
the first data word after the worst-case access delay, including allowance for refresh collisions. The initial latency time and clock speed determine the
latency count setting. Fixed latency is used when the controller cannot monitor WAIT. Fixed latency also provides improved performance at lower clock
frequencies.
VIH
CLK
VIL
VIH
A[22:16]
VIL
VIH
ADV _VIL
VIH
CS _VIL
VIH
OE _VIL
VIH
WE
VIL
VIH
LB/UB
VIL
VOH
WAIT
VOL
VIH
A/DQ[15:0]
VIL
Address
Valid
High-Z
Address
Valid
VOH
VOL
D[0]
Additional WAIT states inserted to allow refresh completion.
D[1]
D[2] D[3]
Don’t Care
Figure 14. Refresh Collision During Variable-Latency READ Operation
NOTE :
1) Non-default BCR settings for refresh collision during variable-latency READ operation:
2) Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
8.2 Functional Description (Synch. mode)
Undefined
Burst Mode
BCR[15] = 0
Standby
No operation
Initial burst read
Power
Standby
Idle
Active
CLK ADV
CS
L
H
H
L
X
L
L
L
OE
WE
CRE
UB /
LB
WAIT A/DQ[15:0] Notes
X
X
L
X
High-Z
High-Z
4
X
X
L
X
Low-Z
X
4
X
H
L
L
Low-Z Address
Initial burst write
Active
L
L
H
L
L
X
Low-Z Address
Burst continue
Burst suspend
Configuration register
write
Configuration register
read
Active
Active
Active
Active
H
L
X
X
X
L
Low-Z
Data in or
Data out
3
X
X
L
H
X
X
X
Low-Z
High-Z
3
L
L
H
L
H
X
Low-Z
High-Z
L
L
L
H
H
L
Low-Z
Config.
reg.out
NOTE :
1) CLK must be LOW during async read and async write modes.
2) When LB and UB are in select mode (LOW), A/DQ[15:0] are affected. When only LB is in select mode, A/DQ[7:0] are affected. When only UB is in the select mode, A/
DQ[15:8] are affected.
3) The device will consume active power in this mode whenever addresses are changed.
4) When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
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