K5N1229ACD-BQ12 Datasheet, PDF (16/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
Command Definitions
Write to Buffer ¹⁵⁾
Program buffer to Flash ¹⁵⁾
Write to Buffer Abort Reset ^16),20)
Set Burst Mode Configuration Register ^17),18)
Set Extended Configuration Register ^17),19)
Enter OTP Block Region
Exit OTP Block Region
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Cycle
3
1
3
3
3
3
4
1st Cycle 2nd Cycle 3rd Cycle
555H
2AAH
BA
AAH
55H
25H
BA
29H
555H
2AAH
XXX
AAH
55H
F0H
555H
2AAH NOTE 18
AAH
55H
C0H
555H
2AAH NOTE 19
AAH
55H
C5H
555H
2AAH
XXX
AAH
55H
70H
555H
2AAH
555H
AAH
55H
75H
4th Cycle
BA
WC
XXX
00H
5th Cycle
PA
PD
6th Cycle
WBL
PD
NOTE :
1) RA : Read Address , PA : Program Address, RD : Read Data, PD : Program Data , BA : Block Address (A24 ~ A14), DA : Bank Address (A24 ~ A21)
ABP : Address of the block to be protected or unprotected , DI :Die revision ID, CR : Configuration Register Setting,
WBL : Write Buffer Location, WC : Word Count
2) The 4th cycle data of autoselect mode and RD are output data. The others are input data.
3) Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, WC and Device ID.
4) Unless otherwise noted, address bits A24–A11 are don’t cares.
5) The reset command is required to return to read mode.
If a bank entered the autoselect mode during the erase suspend mode, writing the reset command returns that bank to the erase suspend mode.
If a bank entered the autoselect mode during the program suspend mode, writing the reset command returns that bank to the program suspend mode.
If DQ5 goes high during the program or erase operation, writing the reset command returns that bank to read mode or erase suspend mode if that
bank was in erase suspend mode.
6) The 3rd and 4th cycle bank address of autoselect mode must be same.
Device ID Data : Top(3010H), Bottom(3011H), Uniform(3012H)
7) Normal Block Protection Verify : 00H for an unprotected block and 01H for a protected block.
OTP Block Protect verify (with OTP Block Address after Entering OTP Block) : 00H for unlocked, and 01H for locked.
8) 0H for handshaking, 1H for non-handshaking
9) The unlock bypass command sequence is required prior to this command sequence.
10) The system may read and program in non-erasing blocks when in the erase suspend mode.
The system may enter the autoselect mode when in the erase suspend mode.
The erase suspend command is valid only during a block erase operation, and requires the bank address.
11) The erase/program resume command is valid only during the erase/program suspend mode, and requires the bank address.
12) This mode is used only to enable Data Read by suspending the Program operation.
13) Set ABP(Address of the block to be protected or unprotected) as either A6 = VIH, A1 = VIH and A0 = VIL for unprotected or A6 = VIL, A1 = VIH
and A0 = VIL for protected.
14) Command is valid when the device is in Read mode or Autoselect mode.
15) For Buffer Program, Firstly Enter "Write to Buffer" Command sequence and then Enter Block Address and Word Count which is the number of word
data will be programmed. Word Count is smaller than the number of data wanted to program by one, Example if 15 words are wanted to program
then WC (Word Count) is 14. After Entering Command, Enter PA/PD’s (Program Addresses/ Program Data). Finally Enter "Program buffer to Flash"
Command sequence, This starts a buffer program operation. This Device supports 512-word Buffer Program.
There is some caution points.
- The number of PA/PD’s which are entered must be same to WC+1
- PA’s which are entered must be same A24~A9 address bits because Buffer Address is A24~A9 address and decided by PA entered firstly.
- If PA which are entered isn’t same Buffer Address, then PA/PD which is entered may be ignored and this buffer programming operation is aborted.
To return to normal operation, hardware reset or "Write to Buffer Abort Reset" command is issued.
- Overwrite for program buffer is also prohibited.
16) Command sequence resets device for next command after aborted write-to-buffer operation.
17) See "Set Burst Mode Configuration Register" for details.
18) On the third cycle, the data should be "C0h", address bits A10-A0 should be 101_0101_0101b, and address bits A21-A11 set the code to be latched.
19) On the third cycle, the data should be "C5h", address bits A10-A0 should be 101_0101_0101b, and address bits A21-A11 set the code to be latched.
20) After software reset and write to buffer abort reset command, min. 5us recovery time is needed for normal read mode.
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