K5N1229ACD-BQ12 Datasheet, PDF (95/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
6.12 Device Identification Register
The DIDR provides information on the device manufacturer, generation and the specific device configuration. This register is read-only. The DIDR is
accessed with CRE HIGH and A[19:18] = 01b, or through the register access software sequence with A/DQ = 0002h on the third cycle.
[Table 6] Device Identification Register Mapping
Bit Field
DIDR[15]
DIDR[14:11]
Field name
Row Length
Device version
Length
Bit
Setting
Version
Bit
Setting
Options
512 words
1b
4th
0110
DIDR[10:8])
Device density
Density
Bit
Setting
128Mb
011b
DIDR[7:5]
UtRAM generation
Generation
Bit
Setting
UtRAM2
010b
DIDR[4:0]
Vendor ID
Bit
Setting
01100
CRE
ADV
A[22:16]
(Except A[19:18])
tAVS
tVP
tAVH
OPCODE
ADDRESS
A[19:18]
CS
OE
WE
Select Control Register
Initiate control register access
tCPH
ADDRESS
tCW
tWP
Write address bus value to control register
LB/UB
A/DQ[15:0]
tAVS
OPCODE
tAVH
ADDRESS
Data
Valid
Don’t Care
Figure 4. Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation
NOTE :
1) A[19:18] = 00b to load RCR, and 10b to load BCR.
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