K5N1229ACD-BQ12 Datasheet, PDF (106/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
11.0 TIMING DIAGRAMS
11.1 Asynchronous READ (CS controlled)
Rev. 1.0
MCP Memory
ADV ^VIH
VIL
VIH
A[22:16]
VIL
VIH
CS
VIL
VIH
UB/ LB _VIL
VIH
OE _VIL
tRC
tAADV
tVP
Valid Address
tAVS
tCVS
tAVH
tCO
tBA
tOE
tOLZ
tCPH
tHZ
tBHZ
tOHZ
tVP
Valid Address
tAVS
tCVS
tAVH
tOLZ
VIH
WE _VIL
VIH
A/DQ[15:0]
VIL
Valid Address
tAA
VOH
VOL
tAVS tAVH
Valid output
VOH
Valid Address
VOL
tAVS tAVH
Don’t Care
Undefined
NOTE :
1) Don’t care must be in VIL or VIH.
2) tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
3) At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
4) tOE(max) is met only when OE becomes enabled after tAA(max).
5) If invalid address signals shorter than min. tRC are continuously repeated for over 2.5us, the device needs a normal read timing(tRC) or needs to sustain standby state for
min. tRC at least once in every 2.5us.
11.1.1 Address Skew for Asynchronous Operation
ADDRESS
ADDRESS
CS
tSKEW
tSKEW
tSKEW
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