K5N1229ACD-BQ12 Datasheet, PDF (43/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
SWITCHING WAVEFORMS
Erase Operation
tAS
Erase Command Sequence (last two cycles)
tWEA
AVD
A16:A24
A/DQ0:
A/DQ15
CE
tAVDP
tAH
2AAh
55h
BA
555h for
chip erase
BA
10h for
chip erase
30h
tDS
tDH
Read Status Data
VA
VA
VA
In
Progress
VA
Complete
OE
tCH
tWP
WE
CLK
tCS
VIL
tVCS
tWPH
tWC
VCC
NOTE :
1) BA is the block address for Block Erase.
2) Address bits A16–A24 are don’t cares during unlock cycles in the command sequence.
3) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
tBERS
Figure 14. Chlp/Block Erase Operations
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