K5N1229ACD-BQ12 Datasheet, PDF (22/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
4.15 Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 512-word in one programming operation. This results in faster effective programming
time than the standard programming algorithms. The Write Buffer Programming command sequence is initi-ated by first writing two unlock cycles. This is
followed by a third write cycle containing the Write Buffer Load command written at the block address in which programming will occur. The fourth cycle
writes the block address and the number of word locations, minus one, to be programmed. For example, if the system will program 19 unique address
locations, then 12h should be written to the device. This tells the device how many write buffer addresses will be loaded with data. The number of loca-
tions to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be pro-
grammed. The write-buffer-page is selected by address bits A24(max.) ~ A9 entered at fifth cycle. All subsequent address/ data pairs must fall
within the selected write-buffer-page, so that all subsequent addresses must have the same address bit A24(max.) ~ A9 as those entered at
fifth cycle. Write buffer locations may be loaded in any order.
Once the specified number of write buffer locations have been loaded, the system must then write the "Program Buffer to Flash" com mand at the block
address. Any other command address/data combination aborts the Write Buffer Programming operation. The device then begins programming. Data poll-
ing should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine
the device status during Write Buffer Programming. The write-buffer programming operation can be suspended using the standard program suspend/
resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command.
Note also that an address loaction cannot be loaded more than once into the write-buffer-page.
The Write Buffer Programming Sequence can be aborted in the following ways:
• Loading a value that is greater than the buffer size(512-word) during then number of word locations to Program step.
(In case, WC > 1FFH @Table 8)
• The number of Program address/data pairs entered is different to the number of word locations initially defined with WC (@Table 8)
• Writing a Program address to have a different write-buffer-page with selected write-buffer-page
( Address bits A24(max) ~ A9 are different)
• Writing non-exact "Program Buffer to Flash" command
The abort condition is indicated by DQ1 = 1, DQ7 = DATA (for the last address location loaded), DQ6 = toggle, and DQ5=0. A "Write-to-Buffer-Abort
Reset" command sequence must be written to reset the device for the next operation. Note that the third cycle of Write-to-Buffer-Abort Reset command
sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode.
And from the third cycle to the last cycle of Write to Buffer command is also required when using Write-Buffer-Programming features in Unlock Bypass
mode. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the DQ7 and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1."
4.16 Accelerated Write Buffer Programming
The device provides accelerated Write Buffer Program operations through the Vpp input. Using this mode, faster manufacturing throughput at the factory
is possible. When VID is asserted on the Vpp input, the device temporarily unprotects any protected blocks, and uses the higher voltage on the input to
reduce the time required for program operations. In accelerated Write Buffer Program mode, the system must enter "Write to Buffer" and "Program Buffer
to Flash" command sequence to be same as them of normal Write Buffer Programming. Note that the third cycle of "Write to Buffer Abort Reset" com-
mand sequence is required in an accelerated mode.
Note that Read While Accelerated Write Buffer Program and Program suspend mode are not guaranteed.
• Program/Erase cycling must be limited below 100cycles for optimum performance.
• Ambient temperature requirements : T_A = 30°C±10°C
4.17 Chip Erase
To erase a chip is to write 1′s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus cycles to write the
command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two more write cycles prior to writing the chip
erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory for an all zero data pattern prior to erasing. The
automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when DQ7 is "1". After that the device returns
to the read mode.
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