K5N1229ACD-BQ12 Datasheet, PDF (17/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
4.0 DEVICE OPERATION
The device has inputs/outputs that accept both address and data information. To write a command or command sequence (which includes programming
data to the device and erasing blocks of memory), the system must drive CLK, AVD and CE to VIL and OE to VIH when providing an address to the device,
and drive CLK, WE and CE to VIL and OE to VIH when writing commands or data.
The device provides the unlock bypass mode to save its program time for program operation. Unlike the standard program command sequence which is
comprised of four bus cycles, only two program cycles are required to program a word in the unlock bypass mode. One block, multiple blocks, or the
entire device can be erased. Table 17 indicates the address space that each block occupies. The device’s address space is divided into sixteen banks. A
“bank address” is the address bits required to uniquely select a bank. Similarly, a “block address” is the address bits required to uniquely select a block.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specifi-
cation tables and timing diagrams for write operations.
4.1 Read Mode
The device automatically enters to asynchronous read mode after device power-up. No commands are required to retrieve data in asynchronous mode.
After completing an Internal Program/Erase Routine, each bank is ready to read array data. The reset command is required to return a bank to the read(or
erase-suspend-read)mode if DQ5 goes high during an active program/erase operation, or if the bank is in the autoselect mode.
Sync MRS option (Extended Configuration Register)
The synchronous(burst) mode will automatically start on the rising edge of the CLK input while AVD is held low after Extended Mode Register
Setting to A13=0, A12=1. If several CLKs exist in AVD low, the last rising edge is valid CLK.
4.1.1. Asynchronous Read Mode
For the asynchronous read mode a valid address should be asserted on A/DQ0-A/DQ15 and A16-A24, while driving CLK and AVD and CE to VIL. WE and
OE should remain at VIH. Note that CLK must remain low for asynchronous read mode. The address is latched at the rising edge of AVD, and then the
system can drive OE to VIL. The data will appear on A/DQ0-A/DQ15. Since the memory array is divided into sixteen banks, each bank remains enabled
for read access until the command register contents are altered.
Address access time (tAA) is equal to the delay from valid addresses to valid output data. The chip enable access time(tCE) is the delay from the falling
edge of CE to valid data at the outputs. The output enable access time(tOE) is the delay from the falling edge of OE to valid data at the output. The asyn-
chronous access time is measured from a valid address, falling edge of AVD or falling edge of CE whichever occurs last. To prevent the memory content
from spurious altering during power transition, the initial state machine is set for reading array data upon device power-up, or after a hardware reset.
4.1.2. Synchronous (Burst) Read Mode
The device is capable of continuous linear burst operation and linear burst operation of a preset length. For the burst mode, the system should
determine how many clock cycles are desired for the initial word(tIAA) of each burst access and what mode of burst operation is desired using
"Burst Mode Configuration Register" command sequences. See "Set Burst Mode Configuration" for further details. The status data also can be
read by synchronous read mode with a bank address which is programming or erasing. This status data by synchronous read mode can be
output and sustained until the system asserts CE high or RESET low or AVD low in conjunction with a new address. To initiate the synchro
nous read again, a new address and AVD pulse is needed after the host has completed status reads or the device has completed the pro
gram or erase operation.
4.1.2.1 . Continuous Linear Burst Read
Sync MRS option (Extended Configuration Register)
The synchronous(burst) mode will automatically start on the rising edge of the CLK input while AVD is held low after Extended Mode Register
Setting to A13=0, A12=1. If several CLKs exist in AVD low, the last rising edge is valid CLK.
The initial word is output tIAA after the rising edge of the last CLK cycle. Subsequent words are output tBA after the rising edge of each successive clock
cycle, which automatically increments the internal address counter. Note that the device has internal address boundary that occurs every 16 words. When
the device is crossing the first word boundary, additional clock cycles are needed before data appears for the next address. The number of additional
clock cycle can vary from zero to thirteen cycles, and the exact number of additional clock cycle depends on not olny the starting address of burst read but
also programmable wait state setting. The RDY output indicates this condition to the system by pulsing low. The device will continue to output sequential
burst data, wrapping around to address 000000h after it reaches the highest addressable memory location until the system asserts CE high or RESET
low or AVD low in conjunction with a new address.(See Table 7.) The reset command does not terminate the burst read operation. When it accesses the
bank is programming or erasing, continuous burst read mode will output status data. And status data will be sustained until the system asserts CE high or
RESET low or AVD low in conjunction with a new address. Note that at least 10ns is needed to start next burst read operation from terminating pre-
vious burst read operation in the case of asserting CE high.
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