K5N1229ACD-BQ12 Datasheet, PDF (92/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
6.5 Drive Strength (BCR[5:4]) Default = 1/2 Drive Strength
The optimization of output driver strength is possible to adjust for the different data loadings. The device can minimize the noise generated on the data
bus during read operation. The device supports full, 1/2 and 1/4 driver strength. The device’s default mode is 1/2 driver strength. Outputs are configured
at 1/2 drive strength during testing.
[Table 2] Drive Strength
Driver Strength
Full
1/2
1/4
1/8
Impedance(typ.)
25~30Ω
50Ω
100Ω
TBD
Recommendation
CL = 30pF to 50pF
CL = 15pF to 30pF
108 MHz at light load
CL = 15pF or lower
CL = 15pF or lower
NOTE :
1) Impedance values are typical values, not 100% tested.
6.6 WAIT Configuration (BCR[8]) Default = 1 CLK Prior.
The WAIT signal is output signal indicating the status of the data on the bus whether or not it is valid. WAIT configuration is to decide the timing when
WAIT asserts or desserts. WAIT asserts (or desserts) one clock prior to the data when A/DQ8 is set to 1. (WAIT asserts (or desserts) at data clock when
A/DQ8 is set to 0). WAIT polarity is to decide the WAIT signal level at which data is valid or invalid. Data is valid if WAIT signal is high when A/DQ10 is set
to 0. (Data is valid if WAIT signal is low when A/DQ10 is set to 1). All the timing diagrams in this SPEC are illustrated based on following setup; A/DQ[10]:0
and A/DQ[8]:1.
Below timing shows WAIT signal’s movement when word boundary crossing happens in No-wrap mode
6.7 WAIT Polarity (BCR[10]) Default = Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT signal requires a pull-
up or pull-down resistor to maintain the de-asserted state.
No-Wrap. Word-line Crossing. LATENCY : 2. WP : Low Enable
CLOCK
0
1
2
3
4
5
6
7
8
9 10 11 12 13
ADV
A/DQ
Valid
Address
D509 D510 D511
Word-line Crossing period
(Only exists in No-wrap mode or Continuous mode)
D512 D513 D514 D515 D516
D517
D518
WAIT
A/DQ[8]:1
1CLK
de-assertion
1CLK
1CLK
assertion
de-assertion
WAIT
A/DQ[8]:0
de-assertion
assertion
de-assertion
Figure 1. WAIT Configuration During Burst Operation
NOTE :
1)Non-default BCR setting: WAIT active LOW.
6.8 Operating Mode (BCR[15]) Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation.
6.9 Latency Counter (BCR[13:11]) Default = 3 Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data value transferred. For
allowable latency codes.
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