K5N1229ACD-BQ12 Datasheet, PDF (32/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
12.0 AC TEST CONDITION
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
Address to Address Skew
Value
0V to VCC
3ns(max)@66Mhz, 2.5ns(max)@83Mhz, 1.5ns(max)@108Mhz, 1ns(max)@133Mhz
VCC/2
CL = 30pF
3ns(max)
VCC
VCC/2
Input & Output
Test Point
VCC/2
0V
Input Pulse and Test Point (including CLK characterization)
Device
Under
Test
* CL = 30pF including scope
and Jig capacitance
Output Load
13.0 AC CHARACTERISTICS
13.1 Synchronous/Burst Read
Parameter
Initial Access Time
Burst Access Time Valid Clock to Output Delay
AVD Setup Time to CLK
AVD Hold Time from CLK
AVD High to OE Low
Address Setup Time to CLK
Address Hold Time from CLK
Data Hold Time from Next Clock Cycle
Output Enable to RDY valid
CE Disable to High Z
OE Disable to High Z
CE Setup Time to CLK
CE Enable to RDY active
CLK to RDY Setup Time
RDY Setup Time to CLK
CLK period
CLK High or Low Time
CLK Fall or Rise Time
Symbol
t_IAA
t_BA
t_AVDS
t_AVDH
t_AVDO
t_ACS
t_ACH
t_BDH
t_OER
t_CEZ
t_OEZ
t_CES
t_RDY
t_RDYA
t_RDYS
t_CLK
t_CLKH/L
t_CLKHCL
1C
(66 MHz)
Min Max
-
95
-
11
5
-
2
-
0
-
5
-
6
-
3
-
-
11
-
9
-
9
6
-
-
11
-
11
3
-
15.1
-
0.4x
t_CLK
-
0.6x
t_CLK
3
1D
(83 MHz)
Min
Max
-
95
-
9
4
-
2
-
0
-
4
-
5
-
3
-
-
9
-
9
-
9
4.5
-
-
9
-
9
3
-
12.05
-
0.4x
t_CLK
-
0.6x
t_CLK
2.5
1E
(108 MHz)
Min Max
-
95
-
7
3.5
-
2
-
0
-
3.5
-
2
-
2
-
-
7
-
9
-
9
4
-
-
7
-
7
2
-
9.26
-
0.4x
t_CLK
-
0.6x
t_CLK
1.5
1F
(133 MHz)
Min Max
-
95
-
6
2.5
-
2
-
0
-
2.5
-
2
-
2
-
-
6
-
9
-
9
3.5
-
-
6
-
6
2
-
7.52
-
0.4x
t_CLK
-
0.6x
t_CLK
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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