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K5N1229ACD-BQ12 Datasheet, PDF (90/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash
datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
6.0 CRE (CONTROL REGISTER ENABLE)
The configuration register values are written via A/DQ pins. In an asynchronous WRITE, the values are latched into the configuration register on the rising
edge of ADV, CS, or WE, whichever occurs first; LB and UB are “Don’t Care.” For reads, address inputs other than A[19:18] are “Don’t Care,” and register
bits 15:0 are output as data (ADV HIGH) on A/DQ[15:0]. Immediately after performing a configuration register READ or WRITE operation, reading the
memory array is highly recommended.
6.1 Bus Configuration Register
The BCR defines how the device interacts with the system memory bus. The BCR is accessed with CRE HIGH and A[19:18] = 10b, or through the register
access software sequence with A/DQ = 0001h on the third cycle.
A19~A18
A/DQ15
A/DQ14
A/DQ13~A/DQ11
A/DQ10 A/DQ8
A/DQ5~A/DQ4
A/DQ3
A/DQ2~A/DQ0
RS
OM
IL
LC
WP
WC
DS
BW
BL
Register Select
A19 A18
RS
0
0
RCR
1
0
BCR
0
1
DIDR
Operating Mode
A/DQ15
OM
0
Synch.
1
Asynch (default)
Initial Latency
A/DQ14
IL
0
Variable (default)
1
Fixed
A/DQ13
0
0
0
0
1
1
1
1
Latency Count
A/DQ12 A/DQ11
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
LC
Reserved
Reserved
2
3 (default)
4
5
6
Reserved
Wait Polarity
A/
DQ10
WP
0
Active Low
1
Active High
(default)
Wait Config.
A/
DQ8
WC
0
at data
1
1 CLK prior
(default)
Driver Strength
A/DQ5
A/
DQ4
DS
0
0
Full Drive
0
1
1/2 Drive
(default)
1
0
1/4 Drive
1
1
1/8 Drive
Burst Wrap
A/DQ3 BW
0
Wrap
1
No Wrap
(default)
NOTE :
1) A/DQ6, A/DQ7, A/DQ9, A16, A17, A20~A22 are reserved and should be ’0’
2) The registers are set automatically to default value.
3) Refresh command will be denied during continuous operation. CS low should not be longer than tBC(tCSM max. 2.5us)
4) If the register code is invalid, register will be set to default value.
A/
DQ2
0
0
0
1
1
Burst Length
A/
A/
DQ1 DQ0
BL
0
1
4 word
1
0
8 word
1
1
16 word
0
0
32 word
1
1
Continuous
(default)
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