K5N1229ACD-BQ12 Datasheet, PDF (42/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
SWITCHING WAVEFORMS
Buffer Program Operations
Buffer Program Command Sequence Word Count
tAS
Program Address/Data pairs (WC+1) "Buffer to Flash"
AVD
A16:A24
tAH
tAVDP
BA
BA
PA_0
PA_1
PA_N
BA
A/DQ0:
A/DQ15
CE
555h A0h 2AAh 55h BA 25h BA WC PA_0 PD_0 PA_1 PD_1
tDS
PA_N PD_N BA 29h
OE
tWP
WE
CLK
tCS
VIL
tVCS
tWPH
tWC
VCC
NOTE :
1) BA = Block Address, WC = Word Count, PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2) Sequential PA_1, PA_2, ... , PA_N must have same address bits A24(max.) ~ A9 as PA_0 entered firstly
3) The number of Program/Data pairs entered must be same as WC+1 because WC = N.
4) “In progress” and “complete” refer to status of program operation.
5) A16–A24 are don’t care during command sequence unlock cycles.
6) Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported.
Figure 13. Buffer Program Operation Timing
tPGM_BP
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