K5N1229ACD-BQ12 Datasheet, PDF (96/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
CLK
0
1
2
tSP tHD
CRE
ADV
tSP tHD
7
8
9
10
A[22:16]
(Except A[19:18])
tAS
A[19:18]
tAS
CS
OPCODE
tCSP
ADDRESS
tHD
tCPH
ADDRESS
OE
WE
LB/UB
tSP
tHD
A/DQ[15:0]
tSP tHD
OPCODE
Latch Control Register Address
ADDRESS
DataValid
Don’t Care
Figure 5. Configuration Register WRITE, Synchronous Mode Followed by READ ARRAY Operation
NOTE :
1) Non-default BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation:
WAIT active LOW; WAIT asserted during delay.
2) A[19:18] = 00b to load RCR, and 10b to load BCR.
3) CS must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles caused by refresh collisions
require a corresponding number of additional CS LOW cycles.
CRE
ADV
A[22:16]
(Except A[19:18])
A[19:18]
CS
OE
WE
LB/UB
tAVS
tAVH
tAA
tVP
tAVS
tAVH
tAAVD
tLZ
tAA
Select Control
Register
tCO
Initiate Register Access
tOE
tOLZ
tCPH
tHZ
tOHZ
Address
Address
A/DQ[15:0]
CR Valid
Address
DATA
VALID
Don’t Care
Undefined
Figure 6. Register READ, Asynchronous Mode Followed by READ ARRAY Operation
NOTE :
1) A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.
- 96 -