K5N1229ACD-BQ12 Datasheet, PDF (112/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
11.7 Single-Access Burst READ Operation—Variable Latency
VIH
CLK _VIL
VIH
ADV
VIL
VIH
A[22:16] _VIL
VIH
CS _VIL
VIH
OE
VIL
VIH
WE
VIL
VIH
LB/UB
VIL
VOH
WAIT
VOL
VOH
A/DQ[15:0]
VOL
tCLK
tSP tHD
tSP
tHD
Valid Address
tCSP
tAVH
tAHCR
tADVO
tBOE
tHD tHZ
tOHZ
tSP tHD
tSP
tCSW
High-Z
tSP
tHD
Valid Address
tOLZ
tHD
tKHTL
VOH
tACLK
VOL
tKOH
Valid
Output
High-Z
READ Burst Identified
(WE = HIGH)
Don’t Care
NOTE :
1) Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2) Don’t care must be in VIL or VIH.
High-Z
Undefined
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