K5N1229ACD-BQ12 Datasheet, PDF (33/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
SWITCHING WAVEFORMS
13 cycles for initial access shown.
CR setting : A14=1, A13=0, A12=0, A11=1
tCES
7.5ns typ(133MHz).
CE
CLK
AVD
A16-A24
A/DQ0:
A/DQ15
1
2
3
4
5
11 12 13
tAVDS
tAVDS
tAVDO
tAVDH
tACS
Aa
tACH
Aa
tIAA
tBDH
tBA
Da Da+1 Da+2 Da+3 Da+4 Da+5 Da+6
OE
tRDY
RDY
Hi-Z
tOER
tRDYA
tRDYS
Figure 4. Continuous Burst Mode Read (133 MHz)
NOTE : In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.
tCEZ
Hi-Z
Da+n
tOEZ
Hi-Z
11 cycles for initial access shown.
CR setting : A14=0, A13=1, A12=1, A11=1
tCES
9.25ns typ(108MHz).
tCEZ
CE
CLK
1
2
3
4
9
10 11
AVD
A16-A24
A/DQ0:
A/DQ15
tAVDS
tAVDS
tAVDO
tACS
Aa
tAVDH
tACH
Aa
tIAA
OE
tRDY
RDY
Hi-Z
tOER
tRDYA
tBDH
tBA
Hi-Z
Da Da+1 Da+2 Da+3 Da+4 Da+5 Da+6 Da+n
tOEZ
tRDYS
Hi-Z
Figure 5. Continuous Burst Mode Read (108 MHz)
NOTE: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.
- 33 -