K5N1229ACD-BQ12 Datasheet, PDF (94/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
VIH
CLK
VIL
VIH
ADV
VIL
VIH
A[22:16]
VIL
VIH
CS
VIL
A/DQ[15:0] VIH
(READ) _VIL
A/DQ[15:0] ^VIH
(WRITE) VIL
N-1 Cycles N Cycle
tAADV
VALID
ADDRESS
tCO
tAA
VALID
ADDRESS
VALID
ADDRESS
tACLK
VOH
VOL
Valid
Output
tSP tHD
Valid
Output
Valid
Input
Valid
Input
Valid
Output
Valid
Output
Valid
Output
Valid
Input
Valid
Input
Valid
Input
Burst Identified
(ADV = LOW)
Don’t Care
Figure 3. Latency Counter (Fixed Latency)
Undefined
6.11 Partial Array Refresh (RCR[2:0] Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only
that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none
of the array. The mapping of these partitions can start at either the beginning or the end of the address map.
[Table 5] Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
Active Section
Address Space
Size
Density
0
0
0
Full Die
000000h-7FFFFFh
8 Meg x 16
128Mb
0
0
1
One-half die
000000h-3FFFFFh
4 Meg x 16
64Mb
0
1
0
One-quarter of die
000000h-1FFFFFh
2 Meg x 16
32Mb
0
1
1
One-eighth of die
000000h-0FFFFFh
1 Meg x 16
16Mb
1
0
0
None of die
0
0 Meg x 16
0Mb
1
0
1
One-half of die
400000h-7FFFFFh
4 Meg x 16
64Mb
1
1
0
One-quarter of die
600000h-7FFFFFh
2 Meg x 16
32Mb
1
1
1
One-eighth of die
700000h-7FFFFFh
1 Meg x 16
16Mb
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