K5N1229ACD-BQ12 Datasheet, PDF (34/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
SWITCHING WAVEFORMS
13 cycles for initial access shown.
CR setting : A14=1, A13=0, A12=0, A11=1
tCES
7.5ns typ(133MHz).
CE
CLK
AVD
A16-A24
A/DQ0:
A/DQ15
1
2
3
4
tAVDS
tAVDS
tAVDO
tAVDH
tACS
Aa
tACH
Aa
tIAA
11 12 13
tBDH
tBA
D7 D0 D1 D2 D3 D4 D5 D6 D7 D0
OE
tRDY
RDY _Hi-Z
tOER
tRDYA
tRDYS
Figure 6. 8 word Linear Burst Mode with Wrap Around (133 MHz)
NOTE : In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.
13 cycles for initial access shown.
CR setting : A14=1, A13=0, A12=0, A11=1
tCES
7.5ns typ(133MHz).
CE
CLK
AVD
A16-A24
A/DQ0:
A/DQ15
1
2
3
4
10 11 12 13
tAVDS
tAVDS
tAVDO
tAVDH
tACS
Aa
tACH
Aa
tIAA
tBDH
tBA
D7 D0 D1 D2 D3 D4 D5 D6 D7 D0
OE
tRDY
RDY _Hi-Z
tOER
tRDYA
tRDYS
Figure 7. 8 word Linear Burst with RDY Set One Cycle Before Data (Wrap Around Mode, CR setting : A18=1)
NOTE : In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high.
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