K5N1229ACD-BQ12 Datasheet, PDF (103/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
9.0 LOW-POWER OPERATION
9.1 Temperature Compensated Self Refresh
Temperature compensated self refresh (TCSR) allows for adequate refresh at different temperatures. This UtRAM2 device includes an on-chip tempera-
ture sensor that automatically adjusts the refresh rate according to the operating temperature. The device continually adjusts the refresh rate to match
that temperature.
9.2 Partial Array Refresh
Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by
refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth
array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map. READ and WRITE operations
to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become corrupted. When re-enabling addi-
tional portions of the array, the new portions are available immediately upon writing to the RCR.
9.3 AC Input/Output Reference Waveform & AC Output Load Circuit
V_CCQ
Input¹
VccQ/2²
V_SSQ
Test Points
VccQ/2² Output
DUT
Test Points _50Ω
30pF
VccQ/2
NOTE :
1) AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10% to 90%) <1.6ns.
2) Input timing begins at VCCQ/2 and Output timing ends at VCCQ/2.
3) All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b)
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