K5N1229ACD-BQ12 Datasheet, PDF (118/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
11.13 Asynchronous WRITE (CS Controlled)
VIH
ADV _VIL
VIH
A[22:16]
VIL
VIH
CS _VIL
VIH
UB/LB _VIL
VIH
WE _VIL
A/DQ[15:0] ^VIH
VIL
tVS
tVP
tCVS
tAVS
tAVH
Valid Address
tCW
tBSA
tWP
tCPH
tBHA
tAW
Valid Address
tAVS
tAVH
Data Valid
tDW
tDH
tVP
tCVP
tAVS
tAVH
Valid Address
tAVS
tAVH
Valid Address
Don’t Care
NOTE :
1) Don’t care must be in VIL or VIH.
2) A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte
operation or simultaneously asserting UB and LB for double byte operation.
3) tCW is measured from the CS going low to the end of write.
4) tAS is measured from the address valid to the beginning of write.
5) tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
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