K5N1229ACD-BQ12 Datasheet, PDF (105/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
10.3 Burst READ Cycle Timing Requirements
Parameter
Address access time (fixed latency)
ADV access time (fixed latency)
CLK to output delay
Burst OE LOW to output delay
CS HIGH between subsequent burst or operations
Maximum CS pulse width LOW
CS or ADV LOW to WAIT valid
CLK period
Chip select access time (fixed latency)
CS setup time to active CLK edge
Hold time from active CLK edge
Chip desable to DQ and WAIT High-Z output
CLK rise or fall time
CLK to WAIT valid
Output HOLD from CLK
CLK HIGH or LOW time
Output disable to DQ High-Z output
Output enable to Low-Z output
Setup time to active CLK edge
ADV HIGH to OE LOW
Address setup to ADV HIGH
ADV HIGH to CLK Rising
Symbol
t_AA
t_AADV
t_ACLK
t_BOE
t_CBPH
t_CSM
t_CSW
t_CLK
t_CO
t_CSP
t_HD
t_HZ
t_KHKL
t_KHTL
t_KOH
t_KP
t_OHZ
t_OLZ
t_SP
t_ADVO
t_AVH
t_AHCR
108MHz
Min
Max
70
70
7
20
15
2.5
1
7.5
9.26
70
3
2
8
1.6
2
7
2
3
8
5
3
3
2
2
80MHz
Min
Max
70
70
9
20
15
2.5
1
7.5
12.5
70
4
2
8
1.8
2
9
2
4
8
5
3
4
2
2
10.4 Burst WRITE Cycle Timing Requirements
66MHz
Min
Max
70
70
11
20
15
2.5
1
7.5
15
70
5
2
8
2.0
2
11
2
5
8
5
3
5
2
2
Unit Notes
ns
4
ns
4
ns
ns
ns
3
us
3
ns
ns
ns
4
ns
ns
ns
1
ns
ns
ns
ns
ns
1
ns
2
ns
ns
ns
ns
Parameter
Symbol
108MHz
Min
Max
80MHz
Min
Max
CS HIGH between subseuent burst or mixed mode
operations
t_CBPH
15
15
Maximum CS pulse width LOW
t_CSM
2.5
2.5
CS LOW to WAIT valid
t_CSW
1
7.5
1
7.5
Clock period
t_CLK
9.26
12.5
CS setup to CLK active edge
t_CSP
3
4
Hold time from active CLK edge
t_HD
2
2
Chip disable to WAIT High-Z output
t_HZ
8
8
Last clock to ADV LOW (fixed latency)
t_KADV
15
15
CLK rise or fall time
t_KHKL
1.6
1.8
Clock to WAIT valid
t_KHTL
2
7
2
9
CLK HIGH or LOW time
t_KP
3
4
Setup time to activate CLK edge
t_SP
3
3
Address Hold from ADV HIGH
t_AVH
2
2
ADV HIGH to CLK Rising
t_AHCR
2
2
NOTE :
1) The High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.
2) The Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.
3) A refresh opportunity must be provided every tCSM. CS must not remain LOW longer than tCSM.
4) tAA, tAADV, tCO guarantee at min set-up time.
66MHz
Min
Max
15
2.5
1
7.5
15
5
2
8
15
2.0
2
11
5
3
2
2
Unit Notes
ns
3
us
3
ns
ns
ns
ns
ns
1
ns
ns
ns
ns
ns
ns
ns
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