K5N1229ACD-BQ12 Datasheet, PDF (124/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
11.19 4-Word Burst WRITE Operation - Row Boundary Crossing
VIH
CLK
VIL
VIH
ADV _VIL
VIH
A[22:16] _VIL
VIH
LB/UB _VIL
VIH
CS
VIL
VIH
OE
VIL
VIH
WE
VIL
VOH
WAIT
VOL
A/DQ[15:0] ^VIH
IN/OUT _VIL
tCLK
tKHKL
tKP tKP
tSP tHD
tAVS
tAHCR
Valid Address
tAVH
tSP
A
tCSP
tSP tHD
tCSW
tSP tHD
Valid Address
VOH
VOL
WRITE Burst Identified
(OE = HIGH)
tSP tHD
D1
D2
End of Row
tHD
tHD tCBPH
tHZ
High-Z
D3
D4
High-Z
Don’t Care
Undefined
NOTE :
1) Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2) Don’t care must be in VIL or VIH.
3) D2 can be written when CS goes high at Point A.
4) There is no limitation for CS high time during Row Boundary Crossing.
6) There is no ADV low during Row Boundary Crossing.
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