K5N1229ACD-BQ12 Datasheet, PDF (123/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
11.18 Burst WRITE Operation—Fixed Latency Mode
VIH
CLK
VIL
VIH
ADV _VIL
VIH
A[22:16]
VIL
LB/UB ^VIH
VIL
VIH
CS _VIL
tSP tHD
tAHCR
tAVH
Valid Address
tCSP
tCLK
tKP
tSP tHD
tCSM
tKP
tKHKL
tKADV
tCBPH
tHD
VIH
OE _VIL
VIH
WE _VIL
VOH
WAIT _VOL
VIH
A/DQ[15:0]
VIL
tSP tHD
tCSW
High-Z
tSP
tHD
Valid Address
NOTE 2
WRITE Burst Identified
(WE = LOW)
tKHTL
tSP
tHD
D[1]
D[2]
D[3]
tHZ
High-Z
D[4]
Don’t Care
NOTE :
1) Non-default BCR settings for burst WRITE operation in fixed latency mode: Fixed latency; latency code two (three clocks); WAIT active LOW;
WAIT asserted during delay; burst length four; burst wrap enabled.
2) WAIT asserts for LC cycles for both fixed and variable latency. LC = Latency Code (BCR[13:11]).
3) Don’t care must be in VIL or VIH.
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