K5N1229ACD-BQ12 Datasheet, PDF (3/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
1. Features
<Common>
• Operating Temperature : -25°C ~ 85°C
• Package : 56Ball FBGA Type - 8mm x 9.2mm x 1.2mmt
0.5mm ball pitch
<NOR Flash>
• This device has the Sync MRS option only
(Extended Configuration Register)
• Single Voltage, 1.7V to 1.95V for Read and Write operations
• Organization
- 33,554,432 x 16 bit ( Word Mode Only)
• Multiplexed Data and Address for reduction of interconnections
- A/DQ0 ~ A/DQ15
• Read While Program/Erase Operation
• Multiple Bank Architecture
- 16 Banks (32Mb Partition)
• OTP Block : Extra 512-Word block
• Read Access Time (@ CL=30pF)
- Asynchronous Random Access Time : 100ns
- Synchronous Random Access Time :95ns
- Burst Access Time :7ns (108MHz)
• Burst Length :
- Continuous Linear Burst
- Linear Burst : 8-word & 16-word with Wrap
• Block Architecture
- Uniform block part : Five hundred twelve 64Kword blocks
- Boot block part : Four 16Kword blocks and five hundred eleven
64Kword blocks (Bank 0 contains four 16 Kword blocks and thirty-one
64Kword blocks, Bank 1 ~ Bank 15 contain four hundred eighty 64Kword
blocks)
• Reduce program time using the VPP
• Support 512-word Buffer Program
• Power Consumption (Typical value, CL=30pF)
- Synchronous Read Current : 35mA at 133MHz
- Program/Erase Current : 25mA
- Read While Program/Erase Current : 45mA
- Standby Mode/Auto Sleep Mode : 30uA
• Block Protection/Unprotection
- Using the software command sequence
- Last two boot blocks are protected by WP=VIL (Boot block part)
- Last one block (BA511) is protected by WP=VIL (Uniform block part)
- All blocks are protected by VPP=VIL
• Handshaking Feature
- Provides host system with minimum latency by monitoring RDY
• Erase Suspend/Resume
• Program Suspend/Resume
• Unlock Bypass Program/Erase
• Blank Check Feature
• Hardware Reset (RESET)
• Data Polling and Toggle Bits
- Provides a software method of detecting the status of program
or erase completion
• Endurance
- 100K Program/Erase cycles
• Support Common Flash Memory Interface
• Low Vcc Write Inhibit
• Output Driver Control by Configuration Register
<UtRAM2>
• Process technology: CMOS
• Organization: 8M x 16 bit
• Power supply voltage: 1.7V~1.95V
• Three state outputs
• Supports Configuration Register Set
- CRE pin set up
- Software set up
• Supports power saving modes
- PAR (Partial Array Refresh)
- Internal TCSR (Temperature Compensated Self Refresh)
• Supports driver strength optimization
• Support 2 operation modes
- Asynchronous mode
- Synchronous mode
• Random access time:70ns
• Synchronous burst operation
- Max. clock frequency : 108MHz
- Fixed and Variable read latency
- 4 / 8 / 16 / 32 and Continuous burst
- Wrap / No-wrap
- Latency :3(Variable) @ 108MHz
- Burst stop
- Burst read suspend
- Burst write data masking
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