K5N1229ACD-BQ12 Datasheet, PDF (100/128 Pages) Samsung semiconductor – 512Mb (32M x16) Muxed Burst, Multi Bank SLC NOR Flash

datasheet K5N1229ACD-BQ12
Rev. 1.0
MCP Memory
8.0 Burst Mode Operation
8.1 synchronous Mode
8.1.1 Synchronous Burst Read Operation
Burst Read command is implemented when ADV is detected low at clock rising edge. WE should be de-asserted. Burst operation re-starts whenever ADV
is detected low at clock rising edge even in the middle of operation.
8.1.2 Synchronous Burst Write Operation
Burst Write command is implemented when ADV & WE are detected low at clock rising edge. Burst Write operation re-starts whenever ADV is detected
low at clock rising edge even in the middle of Burst Write operation.
CLK
CS
ADV
A[22:16]
OE
Latency Code 3 (4 clocks)
ADD.
VALID
WE
WAIT
LB/UB
ADD.
VALID
A/DQ[15:0]
ADD.
VALID
D[0] D[1] D[2]
D[3]
ADD.
VALID
READ Burst Identified
(WE = HIGH)
Don’t Care
Figure 12. Burst Mode READ (4-word burst)
NOTE :
1) Non-default BCR settings for burst mode READ (4-word burst): Fixed or variable latency;
2) Latency code 3 (4 clocks); WAIT active LOW; WAIT asserted during delay.
3) Diagram in the figure above is representative of variable latency with no refresh collision or fixed-latency access.
Undefined
CLK
CS
ADV
A[22:16]
Latency Code 3 (4 clocks)
ADD.
VALID
WE
ADD.
VALID
WAIT
LB/UB
A/DQ[15:0]
ADD.
VALID
D[0] D[1] D[2] D[3]
ADD.
VALID
WRITE Burst Identified
(WE = LOW)
Figure 13. Burst Mode WRITE (4-word burst)
NOTE :
1) Non-default BCR settings for burst mode WRITE (4-word burst): Fixed or variable latency;
2) Latency code 3 (4 clocks); WAIT active LOW; WAIT asserted during delay.
3) tAS is need to Burst Write Operation_.
Don’t Care
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